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THE BUILDING BLOCKS OF SEMICONDUCTOR ROADMAP
The semiconductor industry has enjoyed the success of doubling (every two years) the number of transistors in a silicon chip, which has allowed semiconductor companies worldwide, to offer novel semiconductor products and solutions. This is exactly what Moore’s law predicted when it was proposed around four decades ago.
Increasing transistor density per given area allows computer systems to cater to multiple (and numerous too) requests at the same time. This is why in 2021 a smartphone is capable of crunching the data that in the 1980s would require a giant server.
However, as the semiconductor world marches towards 3nm mass production (with 2nm already showcased by IBM), there is a growing concern about whether or not Moore’s law will keep pace with the advancement in the technology-node (mainly shrinking transistor size) and what are the alternate solutions.
More-Than-Moore Solutions Have Been In Work For Last Two Decades.
The answer to this problem lies in the different unique solutions that the semiconductor industry has been working around in the last couple of decades. The semiconductor industry knew there is going to be a time when Moore’s law will not be applicable as it is today and a course correction would be needed.
This course correction has led to numerous design to manufacturing changes that have enabled silicon chips to provide more performance and better power consumption without compromising on the area. These solutions have been built on top of different semiconductor product development processes which have come together to drive next-gen workloads without worrying about the future implications of Moore’s law.
Design: To drive innovative solutions that defy Moore’s law by providing similar/better performance and lower power consumption often requires a novel design. These designs can at the circuit level or the system level. The combination of both enables richer design solutions. Like AMD’s chipset-based CPU and GPU design or Appel’s M1 SoC. All these design methodologies drives next-gen solutions that are needed to run future workloads optimally. Such designs often require years of research and development that leads to patents and IP. TVS is another design solution that has allowed novel chip designs.
Node: When it comes to choosing a technology-node for a high-performance device like XPU, the choice is always to go for the best out in the market. This is why companies like TSMC, Samsung, IBM, and Intel are racing to provide the most advanced solution possible. However, the base of the technology-node is a transistor, and to drive a next-gen technology-node that packs more transistor than its predecessor, requires alternate (and better) FET solutions. This is why new scaling CMOS solutions by leveraging new FETs designs is being explored. This started with MBCFETs and soon will move towards forksheet based FETs.
Memory: To drive data-driven workloads efficiently, memory plays a crucial role. As the design changes to accommodate More-Than-Moore solutions, the memory organization and interface also need to change. This has lead companies like Samsung to come up with High Bandwidth Memory (HBM) to power next-gen AI processing solutions. Similarly, Micron has come up with alternate solutions called HBM2E. Advancement in-memory solutions are vital to ensure any Moore-alternate solutions to drive chips are backed up by faster data processing and data transfer.
Package: Silicon chip is nothing but a die from a wafer that gets packaged before being mounted onto the application system. With Moore’s law the internals of the chip was doubling (transistor mainly) to enable more performance, and this has to lead to alternate package technology over the years. This can range from WLCSP to WLFO and beyond. Even the new design methodology of chiplets has to lead to alternate package technology from companies like TSMC, which came up with Chip-on-Wafer-on-Substrate (CoWoS), a 2.5D based package technology to drive next-gen chiplets solutions. To keep up with More-Than-Moore, new package technologies will keep coming out in the market.
Interconnect: As the number of blocks and processing units inside a given chip increases, the need to transfer data faster from one point of the chip to another has also increases. This is why researchers and several companies are focusing on photonics as an alternate. This can ensure the data is not only transferred without adding bottlenecks but also makes sure there is no loss of data. All this while not increasing the power consumption.
Manufacturing: In the end, all design to interconnect process boils down to the fact that whether the solution is manufacturable. New design process and solutions often require close interaction with the equipment manufacturers, FABs and OSATs. This is why, based on years of development, the semiconductor manufacturing industry is moving towards EUV to drive next-gen manufacturing capability. This is going to not only enable 3nm/2nm technology-node but will also drive different package and interconnect solution that have been proposed in the last few years.
Different methodologies discussed above have enabled alternate solutions that leverage Moore’s law but by adapting the new design and manufacturing strategies that ensure there are no bottlenecks.
These solutions range from having a compact chip with all the possible processing blocks to solutions where processing blocks are taken out of the chip and spread across the system. Some solutions also take a different approach of stacking the silicon in such a way that the best of 2D and 3D chip designing comes together to provide a rich user experience.
All these solutions combined are leading the semiconductor industry towards a Moore-Than-Moore world.
THE MORE-THAN-MOORE SEMICONDUCTOR ROADMAP
The semiconductor industry has implemented several solutions that can be considered as an alternate to Moore’s law and also have been around for many years. These alternate solutions focus on how the design and manufacturing process should be handled to ensure there is always a way to drive more power out of the given silicon chip. All these solutions have been designed without focusing much on the transistor density or technology-node.
It will not be wrong to say that in doing so the semiconductor industry has created itself a pathway to drive into the More-Than-Moore world.
Below are the four major milestones in the last couple of decades that have established the roadmap for the More-Than-Moore world. Few of these have been known to the semiconductor industry for a very long time and little emphasis has been given as to whether this design and manufacturing solution can provide a path towards More-Than Moore or not. In reality, the solution indeed provides a way after Moore’s law ends.
System-On-A-Chip – SOC: SOCs have been around for a couple of decades. The need for multi-core systems coupled with graphics, audio, and video processing lead to SOC. SOC allowed different sub-blocks to reside on a single die area and provided a strong challenge to semiconductor designers and manufacturers. The first major reason was the complexity involved in ensuring the design works as expected and the second reason was the ability to produce high-yielding wafers. SOC has had a mix of both the best and the worst of the semiconductor product development process. Some solutions have to see the end of a life well before the planned date and on another hand, some SOC solutions lasted more than their life span. In the end, SOC provided a way to club complex and required solutions in the smallest area with the help of shrinking transistor size. However, this can only last till the power and thermal profile of the solutions makes technical sense and with challenging process development (shrinking transistor size), SOC may not survive the marking for long but during their time allowed a way to club different features under the same die area.
Multi-Chip Modules – MCM: MCM is a step ahead of SOC. It borrows all the ideas of SOC but brings different types of SOC together on a single platform. The communication between different SOC or ICs is then established using the high-speed interface. This has enabled several XPU (Xeons to Ryzen) based solutions that can diversify the design and manufacturing of the blocks and then leverage interface technology to ensure the data communication is as good or at-par with SOC solutions. Many argue that chiplets design is one form of MCM and in the last couple of years chiplets have taken over the SOC world, and MCM is considered to be the true step towards the More-Than-Moore world.
System-In-A-Package – SIP: SIP takes the best of MCM and SOC to come up with chip solutions that allow 3D-based stacking of different blocks. The interposer or TVS has played a pivotal role in enabling SIP. The goal of SIP is to take the 2D area and covert it into 3D by stacking the different blocks of SOC/MCM on top of each other. This way the area consumption decreases which 2D solutions like SOC and MCM cannot achieve without using advanced technology-node. SIP does have a drawback as they suffer from thermal and packaging challenges. With advanced technology-node nearing 1nm, SIP might be the best More-Than-Moore solution to provide an alternative to chip designing compared to MCM and SOC.
System-On-Package – SOP: All the above three More-Than-Moore alternate solutions are designed with the focus that the end system is going to be printed circuit board on top of which the SOC/MCM/SIP system will reside. However, this does not help the smaller devices like smartphones where the goal is to ensure that there is more room for battery by shrinking the board area. To shrink the board footprint, SOP is the best way to design a computing system. SOP takes different chips (either a SOC, MCM, or SIP) and then brings all these individual chips inside a single package. The complexity to achieve an elegant SOP system is way too high. It requires not only synchronization of different types of system/devices (SOC/MCM/SIP) but also a standard interface that can allow packaging of all devices while ensuring that there is no bottleneck or leakage. SOP if done correctly might very well end the need for board and allow a more compact silicon solution while defying Moore’s law.
The above four semiconductor design and manufacturing alternatives certainly provide a way to design chips (mainly XPU) such that there is no need to worry about packing more transistors in the smallest area.
From SoC to SOP, the solutions simply take the silicon area out of the context by bringing different sub-systems together but in a unique way, and it pushes the FABs and OSATs to come up with manufacturing technologies (which many FABs and OSATs already have) that can ensure the sub-systems work seamlessly even though there are disaggregated.
As the semiconductor industry inches towards 1nm technology-node, SOC/MCM/SIP/SOP based chip solutions are certainly going to provide a roadmap for More-Than-Moore solutions.
